1. Field of the Invention
This invention relates generally to data processing systems and more particularly to means for temporary storage of groups of data signals. In modern data processing systems, in order to reduce the number of data paths associated with movement of data, it is frequently desirable to store, temporarily, a portion of a data signal group and replace the stored portion with an abbreviated data group during manipulation, in the data processing unit, for which the temporarily stored data group is irrelevant. As an example, a group of data signals, stored in a peripheral subsystem, and which are to be manipulated by the central processing unit can have a true address. With the present apparatus, the true address can be stored at the interface to the central subsystem, and an identifying data group can be transmitted with the data signal group during manipulation in the central processing unit. Upon return from the central processing unit to the interface, the identifying number can be utilized to provide the true address for restorage of the data group in the peripheral subsystem.
2. Description of the Prior Art
A variety of devices for the temporary storage of groups of data signals is known in the prior art. Cache memory devices provide a good example. The function of the devices is to provide a temporary storage of data signal groups for generally random or non-sequential withdrawal at some later time. Many of the strategies for providing identifying numbers for accessing the stored data groups include associating a particular physical location with a portion of the address. It can, moreover, require an excessive amount of apparatus to store, identify and retrieve data signal groups and subsequently, to store data groups in memory locations of changing availability.
It is therefore an object of the present invention to provide apparatus for improved performance of a data processing system.
It is a further object of the present invention to provide an improved memory unit for temporary storage of data signal groups for use in a data processing unit.
It is a still further object of the present invention to provide a memory unit for temporary storage of groups of data signals which can be entered into and removed from the memory unit in random order.
It is a more particular object of the present invention to provide a memory unit for storage of groups of data signals in a multiplicity of memory locations and for developing signals identifying the memory location, the entire procedure occurring in a single clock cycle.
It is another more particular object of the present invention to provide a memory unit for temporary storage of groups of data signals for which identifying signals applied to the memory unit can cause the removal of a predetermined data signal group in a single clock cycle.
It is a still more particular object of the present invention to provide a first group of memory locations which can be addressed by the contents of a second group of memory locations, the contents of the second group of memory locations providing either a location in the first memory location group available for storage of a group of data signals or data signals identifying the location of a stored data signal group.